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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 59: Configuration Switching Characteristics (Cont’d)
Symbol
Description
-3
Speed Grade
-2 -1
-1L
Units
T SMCKBY
F SMCCK
F RBCCK
F MCCKTOL
CCLK to BUSY out in readback at 2.5V
CCLK to BUSY out in readback at 1.8V
Maximum Frequency with respect to nominal CCLK
Maximum Readback Frequency with respect to
nominal CCLK
Frequency tolerance, master mode with
6
6
100
100
55
6
6
100
100
55
6
6
100
100
55
7
7
70
60
60
ns, Max
ns, Max
MHz, Max
MHz, Max
%
respect to nominal CCLK
Boundary-Scan Port Timing Specifications
T TAPTCK /T TCKTAP
T TCKTDO
F TCK
F TCKB_MIN
TMS and TDI Setup time before TCK/ Hold time
after TCK
TCK falling edge to TDO output valid at 2.5V
TCK falling edge to TDO output valid at 1.8V
Maximum configuration TCK clock frequency
Minimum boundary-scan TCK clock frequency
when using IEEE Std 1149.6 (AC-JTAG). Minimum
3.0/2.0
6
6
66
15
3.0/2.0
6
6
66
15
3.0/2.0
6
6
66
15
4.0/2.0
7
7
33
15
ns, Min
ns, Max
ns, Max
MHz, Max
MHz, Min
operating temperature for IEEE Std 1149.6 is 0°C.
F TCKB
Maximum boundary-scan TCK clock frequency
66
66
66
33
MHz, Max
BPI Master Flash Mode Programming Switching
T BPICCO (2)
ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B
outputs valid after CCLK rising edge at 2.5V
ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B
6
6
6
6
6
6
7
7
ns
ns
outputs valid after CCLK rising edge at 1.8V
T BPIDCC /T BPICCD
T INITADDR
Setup/Hold on D[15:0] data input pins
Minimum period of initial ADDR[25:0] address
cycles
4.0/0.0
3
4.0/0.0
3
4.0/0.0
3
5.0/0.0
3
ns
CCLK cycles
SPI Master Flash Mode Programming Switching
T SPIDCC /T SPIDCCD
T SPICCM
T SPICCFC
T FSINIT /T FSINITH
DIN Setup/Hold before/after the rising CCLK edge
MOSI clock to out at 2.5V
MOSI clock to out at 1.8V
FCS_B clock to out at 2.5V
FCS_B clock to out at 1.8V
FS[2:0] to INIT_B rising edge Setup and Hold
3.0/0.0
6
6
6
6
2
3.0/0.0
6
6
6
6
2
3.0/0.0
6
6
6
6
2
3.5/0.0
7
7
7
7
2
ns
ns
ns
ns
ns
μs
CCLK Output (Master Modes)
T MCCKL
T MCCKH
Master CCLK clock Low time duty cycle
Master CCLK clock High time duty cycle
45/55
45/55
45/55
45/55
45/55
45/55
40/60
40/60
%, Min/Max
%, Min/Max
CCLK Input (Slave Modes)
T SCCKL
T SCCKH
Slave CCLK clock minimum Low time
Slave CCLK clock minimum High time
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
ns, Min
ns, Min
Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK
F DCK
T MMCMDCK_DADDR /
T MMCMCKD_DADDR
Maximum frequency for DCLK
DADDR Setup/Hold
200
1.25/
0.00
200
1.40/
0.00
200
1.63/
0.00
200
1.64/
0.00
MHz
ns
DS152 (v3.6) March 18, 2014
Product Specification
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